High speed serial interface standards

Shield continuity between connecting cables is maintained by the connector housing. All signals are balanced, differentially driven, and received at standard ECL levels. The ECL negative supply voltage, Vee, may be either In the event that the interface cable is not present, the differential ECL receivers must default to a known state. To guarantee this, it is necessary when using the 10H or 10H to add a 1. This allows the proper mvolts minimum to be developed across the ohm resistors and will create a longitudinal termination of ohms.

The default state of all interface signals is deasserted. It is not necessary to use external resistors when using the 10H since it has an internal bias network which will force an output low state when the inputs are left floating.

The interface must not be damaged by an open circuit or short circuit connection on any combination of pins. Source timing is defined as timing waveforms generated at a transmitter. Destination timing is defined as timing waveforms incident at a receiver. The leading edge of the timing pulse shall be defined as the boundary between deassertion and assertion. The trailing edge of the timing pulse shall be defined as the boundary between assertion and deassertion.

At the receiver, once passing through the line receiver, the data should immediately again be reclocked into an ECL flip flop. Control signals do not require the use of a flip-flop. This value is obtained from:. These numbers allow for transmission distortion elements of 1. This leaves 1. The data will be considered valid on the trailing edge. Thus, transmitters clock data out on the leading edge, and receivers clock data in on the trailing edge. This allows an acceptance window for clock-data skew error.

This allows for a ns delay for 15 meters of cable round trip delay. The maximum gapping interval is not specified. A gapping interval is measured as the amount of time between two consecutive clock edges of the same slope. The definition of valid data is application dependent and not a subject of this specification.

This is consistent with HSSI being a layer 1 specification, and therefore having no knowledge of data validity. CA and TA are asynchronous of each other. The solution comes with pre-synthesized and validated IP cores Transmitter and Receiver , demo design, and complete documentation which reduces the design and validation time.

Our website uses cookies including profiling cookies of authorised third parties to give you a better browsing experience, and by continuing to use our site you accept our cookies policy. Find out more on how we use cookies and how you can change your settings by clicking here.

All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Audio, Voice, and Line Circuits Software. Audio, Voice, and Line Circuits Documents.

MyMicrosemi Partner Portal. Xilinx transceivers are positioned to support the wide range of optical rates and form factors. The Versal ACAPs feature a pair of transceivers to support the variety of optical interconnects in the ecosystem today.

By equipping the ARMv8 processors with a transceiver and peripherals to support the most common serial interconnects, Xilinx has simplified the design process and reduced the overhead associated with interfacing to those interconnects. Xilinx provides a broad range of serial IP protocol support to accelerate design productivity:.

The Xilinx Versal and UltraScale Architecture transceiver portfolio delivers exceptional value to customers in the following areas:. You are using a deprecated Browser.

Internet Explorer is no longer supported by Xilinx. Technology High Speed Serial. High Speed Serial.